KOVA1 is the first silicon implementation of the KOVA (KOvilta Vision Array) -architecture.

KOVA1 is a 96x96 pixel focal-plane processor array, manufactured in 180nm CMOS technology. The sensor-processor chip is embedded into a compact smart-camera system with FPGA-based control and Ethernet I/O.

Significant advantages in both processing speed and energy consumption. In the focal plane processor architecture, each pixel-cell of the sensor array contains a programmable processor element, which operates directly on the analog photodiode output. The pixel-parallel processing on the sensor plane enables very high speed, and reduces high-cost (time, energy) long-distance data transfers.

Complex algorithms can be performed completely within the KOVA1 chip. The pixel cells in the array are physically interconnected within their local neighborhoods, allowing direct information exhange in sensor-level image analysis operations. Local, pixel-level memories allow multiple full images or intermediate processing results to be stored on the sensor plane.

Efficient integration to higher level image content analysis systems. The output data from KOVA1 may, at minimum, consist only of an indication of the presence of a desired image property or event (yes/no, 1 bit), or e.g. a set of object coordinates or object features (segmented image). Although original image data can also be read out, if required, a radically reduced amount of output data allows for even greater analysis speeds. With the sensor-processor output containing only high-level data, any further image-content analysis can be implemented with much lower additional hardware requirements.

Efficient pixel-level computation. Kovilta's highly optimized pixel-level processing circuitry employs very efficient analog and digital (mixed-mode) computation to perfom a wide range of programmable operations, ranging from automatic sensor adaptation, grayscale filtering and segmentation to complex object level visual analysis.

Compact embedded camera platform. The KOVA1 embedded camera system includes an Field Programmable Gate Array (FPGA) -chip, which controls the program execution and I/O of the sensor-processor chip. Because the control and I/O structures only consume a small a part of the resources available within the FPGA, it is also possible to implement additional visual analysis operations on the FPGA, to complement the on-chip sensor-level processing.

Autonomous smart camera operation. The camera can be programmed and controlled through Kovilta's KEDE software environment. Programming and data I/O is implemented via an Ethernet connection, while direct CMOS-signal outputs bypassing the network interface are also available. Program code can be stored within (non-volatile) memory inside the camera. The camera can be operated autonomously without any PC-connection, i.e. to provide output data to some other Ethernet-connected or directly controlled device.

More details on the KOVA1 implementation, processing capabilities and performance can be found in the KOVA1 Technote.